Romanian Journal of Information Science and Technology (ROMJIST)

An open – access publication


ROMJIST is a publication of Romanian Academy,
Section for Information Science and Technology

Editor – in – Chief:
Radu-Emil Precup

Honorary Co-Editors-in-Chief:
Horia-Nicolai Teodorescu
Gheorghe Stefan

Secretariate (office):
Adriana Apostol
Adress for correspondence: (after 1st of January, 2019)

Editing of the printed version: Mihaela Marian (Publishing House of the Romanian Academy, Bucharest)

Technical editor
of the on-line version:
Lucian Milea (University POLITEHNICA of Bucharest)

• National Institute for R & D
in Microtechnologies
(IMT Bucharest),
• Association for Generic
and Industrial Technologies (ASTEGI),

ROMJIST Volume 23, No. 4, 2020, pp. 333-353, Paper no. 666/2020

Nicolae Adrian BRAIC, Cristian RADUCAN, Marius NEAG, Marina TOPA, Vlad IONESCU
Ascertaining the root-cause of discrepancies between simulations and measurements for a SC DC-DC converter

ABSTRACT: This paper presents a methodology for ascertaining the root cause of discrepancies between simulation and measurement related to particular parameters and/or features of an integrated circuit. The main idea is to assess the sensitivity of that IC parameter/feature to factors which may not have been accurately and comprehensively considered during pre-silicon verification – such as block-level non-idealities, internal parasitic components and inaccuracies in modeling the package and external components – by running parametric sims on amended views of top-level IC schematic and simulation testbench. Behavioral models of large functional blocks within the IC are employed, not only to reduce the simulation time but also to allow for a quick assessment of the impact block-level non-idealities may have on the IC performance. After identifying the factors that impact most the IC parameter/feature under analysis, the designer can find sets of values/combinations of some of those factors that yield simulation results most similar to the measurement results. Finally, the system layout, the simulation testbenches and the measurement setup are analyzed in detail, focusing on possible root cause(s) of the factors/combination of factors indicated by simulations. A real-case deployment of this methodology is presented: a switched-capacitor DC-DC converter, whose measured output voltage ripple had a different shape and larger amplitude than those predicted by simulations. The proposed methodology can be embedded in the design flow, as well, from deriving block-level parameters from general system requirements to setting clear requirements for layout routing of key tracks within the IC.

KEYWORDS: Microelectronics, verification methodology, analog and mixed-signal IC, root-cause identification, Verilog- A model; switched capacitor DC-DC converter; voltage output ripple

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