ROMJIST Volume 24, No. 84, 2021, pp. 4-27, Paper no. 677/2021
Paul COSTE, Paul MARTARI, Marius NEAG, Marina ȚOPA, Vlad IONESCU Programmable Capacitor Multiplier Based on Gm-cell with Two Outputs – Topology, Circuit Implementations and Applications
ABSTRACT: This paper introduces a novel circuit topology for programmable capacitance multipliers implemented with linear transconductors (Gm cells), along with several circuit implementations and applications. Starting from a fairly well-known architecture, that employs two Gm cells, the proposed topology only requires one transconductor core. It is particularly well suited to high-linearity transconductors, such as the Kwan-Martin and Welland circuits, but simple differential pairs can also be used to implement it. In fact, circuit implementations based on all three transconductor types are demonstrated in the paper. Mathematical analysis and parametric simulations were performed in order to assess the impact non-idealities inherent to circuit implementation may have on the proposed topology. It was found that the finite value of an output resistance was the main performance limiting factor for the capacitance multiplier. Therefore, a compact implementation for active cascoding of current mirrors was used in subsequent circuit implementations. The usefulness of the proposed capacitance multiplier was demonstrated on three applications, designed in a standard 0.18µm CMOS technology: a triangular waveform generator with signal frequency programmable between 2.67kHz and 21.4kHz; a fully differential lossy integrator, with the pole frequency programmable between 75kHz and 575kHz, and the decoupling capacitor of a fully-integrated LDO, with the equivalent value of 100pF derived from a 5pF placed capacitance.KEYWORDS: Read full text (pdf)