ROMJIST Volume 24, No. 4, 2021, pp. 366-383
Gheorghe M. ȘTEFAN Pseudo-Reconfigurable Computing
ABSTRACT: The pseudo-reconfigurable computing we propose is an implementation of heterogeneous computing in the form of a compromise between the realization of accelerators as circuits through reconfiguration techniques using FPGAs and the realization of accelerators as parallel computing structures made in ASIC technology. The proposed solution is implementable in FPGA in the form of a programmable structure that is parameterizable and configurable. The programmable accelerator is a cellular parallel engine with a structure and architecture that efficiently covers most of the parallel computing patterns. The structural and architectural aspects of the proposed system are introduced based on Stephen Kleene’s Partial Recursive Function Model, and evaluated using: (1) Functional Forms introduced by John Backus, (2) ‘dwarfs” listed in the Berkeley’s View of Parallel Landscape, and last but not least (3) patterns already imposed in the practice of parallel computing.Read full text (pdf)