A.C. Bunea, D. Neculoiu, M. Lahti, T. Vähä-Heikkilä
Abstract. In this paper we present the design, electromagnetic simulation and experimental results of a 35 GHz Low Temperature Co-Fired Ceramics (LTCC) antenna and a LTCC grounded coplanar waveguide (GCPW) to stripline (SL) transition. The stripline-fed antenna and the GCPW-to-SL transition are designed for a six-tape LTCC process. For characterization purposes, two back-to-back transitions are fabricated and measured, showing reflection losses lower than – 10 dB between 27 – 46.7 GHz, and insertion losses lower than 1.5 dB in this frequency range. The insertion losses of the back-to-back transition are remarkably low in the whole Ka band (26.5 – 40 GHz), with estimated losses between 0.15 – 0.5 dB for a single transition. The antenna element has four parasitic microstrip patches and a simulated directivity of 8.2 dBi at 35 GHz. The antenna element integrated with the transition is fabricated and characterized on wafer. The integrated structure shows measured reflection losses lower than –10 dB between 34.48 – 36.39 GHz. The transmission characteristic as a function of frequency is recorded and in good agreement with the simulated gain. The overall size of the fabricated antenna with transition is 6.24 x 8.975 mm2, with the standalone antenna element having a size of just 6.24 x 6.15 mm2. Read the pdf
I. Giangu, V. Buiculescu, F. Bechtold, G. Konstantinidis, K. Szaciłowski, A. Stefanescu, K. Pilarczyk, A. Stavrinidis, P. Kwolek, G. Stavrinidis, J. Mech, A. Müller
Abstract. Novel LTCC packages intended for acoustic wave sensing devices chip assembly are proposed in this paper. A single assembly operation was required for both structure models based on DuPont 9K7 “green” tapes, after layout design and interactive 3-D electromagnetic optimization processes. Due to LTCC manufacturing technology, a large number of package structures containing cavities, inner vertical and horizontal interconnects, pads for inner components’ assembly and external signal connections was manufactured. Surfaces acoustic wave (SAW) resonators and film bulk acoustic resonator (FBAR) structures have been used with very good results as temperature and, respectively, humidity sensing devices. Input and output signal ports have been define as coplanar transmission line (CPW) configuration for a good impedance matching to the measuring system. Linear behavior of the frequency shift vs. temperature and, respectively, relative humidity was evidenced. Although certain temperature sensitivity reduction is observed, an improved dynamic range of the return loss response is noticed for packaged SAW devices, favorable for subsequent signal processing and temperature value extracting. Very small and complex RF packages, with SMT compatible and solderable AgPt pinout and two different levels of Au pads for Au wire bonding inside the cavity intended to provide handling protection after wire bonding are the main outcome of this paper. Read the pdf.
R. Pascu, G. Pristavu, F. Craciunoiu, M. Badila, M. Kusko, G. Brezeanu, J. Neamtu, R. Gavrila
Abstract. The effect of post-oxidation annealing (POA) treatments on SiC based MOS capacitor characteristics have been investigated up to 623K, targeting operation in high temperature applications. In order to achieve the passivation of the SiO2/4H-SiC interface and to reduce flat band voltage (VFB) instabilities with temperature, the POA in POCl3 ambient was used. The structures subjected to POA were comparatively analysed with the as-oxidized ones. High frequency capacitance-voltage (C-V) measurements were performed both at room and high temperatures on wafer and encapsulated samples. The C-V characteristics show an improved stability of VFB with temperature for POCl3 based POA samples: while the as-oxidized structures show a linear decrease of VFB after 423K, the POA leads to an increase of the temperature range where VFB is approximately constant (up to 623K). Read the pdf.
I. Vornicu, R. Carmona-Galán, Á. Rodríguez-Vázquez
Abstract. The design of a CMOS image sensor based on single-photon avalanche-diode (SPAD) array with in-pixel time-to-digital converter (TDC) is presented. The architecture of the imager is thoroughly described with emphasis on the characterization of the TDCs array. It is targeted for 3D image reconstruction. Several techniques as fast quenching/recharge circuit with tunable dead-time and time gated-operation are applied to reduce the noise and the power consumption. The chip was fabricated in a 0.18μm standard CMOS process and implements a double functionality: time-of-flight (ToF) estimation and photon counting. The imager features a programmable time resolution of the array of TDCs down to 145ps. The measured accuracy of the minimum time bin is lower than ±1LSB DNL and ±1.7LSB INL. The TDC jitter over the full dynamic range is less than 1LSB. Read the pdf.
F. Bîzîitu, M.-I. Serban, C. Murtaza
Abstract. The proposed circuit is a dual-chain Dickson type charge pump making use of both active and passive charge transfer switches in order to achieve a compromise between power efficiency, circuit complexity and device reliability. The charge pump is capable of sourcing up to 500µA at 10V output voltage for supplying the error amplifiers of two NMOS Low Drop Out (LDO) linear regulators as part of a high integration automotive IC. Read the pdf.
R. TUDOR, M. KUSKO, C. KUSKO, F. CRACIUNOIU, A. AVRAM, D. VASILACHE, A. DINESCU
Abstract. In this paper we are molding the phase profile of a Gaussian beam in order to achieve a phase singularity called optical vortex. For this purpose, we apply the beam shaping technique for a 635 nm wavelength radiation using a diffractive optical element with high diffractive efficiency. We use reflective spiral phase plates and fork-like computer generated holograms, fabricated with photolithographic processes and electron beam lithography, respectively. Uniform ring intensity is achieved in the optical vortex configurations and also zero intensity where the phase is undefined. Phase singularities interferences are done using a Michelson interferometer. Beam shaping simulations results based on the Kirchhoff integral are in concordance with experimental results. Read the pdf.
G. Boldeiu, V. Moagar-Poladian, T. Sandu
Abstract. Extensive numerical calculations show that the capacitance of back-gated nanowires with various degrees of dielectric embeddings is accurately described with an effective dielectric constant as long as the difference between the dielectric thickness and the gate-nanowire distance is held constant. This is valid for dielectrics with permittivities ranging from simple air to water. However, due to screening the scaling is not valid if the dielectric lies down well below the nanowire. Moreover, when only the dielectric thickness varies the capacitance characteristics are S-shaped with three distinct regions, of which only the first two can be used for dielectric sensing. The first region is almost linear while the middle region, with a span of two diameters around the center of the nanowire, is the most sensitive. Read the pdf.
V. Banu, P. Godignon, M. Alexandru, J. Montserrat,
Abstract. This work demonstrates a functional fabricated high temperature compensated Voltage Reference (VR) integrated circuit on 4H-SiC material. The study starts with an experimental analysis on the feasibility on silicon carbide (SiC) of the widely used bandgap reference concept both with Schottky and bipolar diodes. Then an original solution is proposed for a special finger type MESFET. Our approach of the MESFET design overcomes the typical embedded drain leakage of finger type MESFET. This device design was specially developed for using in analog schematics on SiC. Further, an original VR schematic is proposed avoiding the bandgap reference topology and accordingly avoiding an operational amplifier (OpAmp), which is not yet developed on SiC. The performed measurements on the fabricated integrated circuits show a temperature coefficient (TC) comparable to the normal bandgap voltage references on silicon but this SiC circuit is able to work up to 300ºC, compared to 125ºC for silicon or 200ºC for SOI (silicon on insulator). A very important progress of our work is the integration of the presented circuit on the same SiC chip with a power lateral MESFET. Additionally, the circuit contains a linear temperature sensor useful for over temperature protection. Read the pdf.