Improved Linearity Active Resistors Using MOS and Floating-Gate MOS Transistors

A new linearity improvement technique for a CMOS active resistor will be presented, using an anti-parallel connection of two quasi-identical active resistor structures, different biased and opposite excited. The second-order effects that affect the MOS transistor operation will be also taking into account, the proposed linearization method compensating also the linearity degradation imposed by these effects. In order to minimize the silicon area, an original method based on an optimal implementation of the current-controlled voltage generator will be presented. Additionally, the replacing of classical MOS transistors by FGMOS (Floating Gate MOS) active devices will further reduce the circuit complexity, and, thus, the area occupied on silicon, having the result of about two order of magnitude reducing area with respect to a classical resistor. The circuit estimated linearity error is under 1% for an extended input range of ± 500 mV and for a small value of the supply voltage, VCC = ± 3V. The proposed active resistor is designed for low-voltage low-power applications and it is implemented in 0.35 mm CMOS technology, the SPICE simulations confirming the theoretical estimated results.